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BENEFITS
DATA SHEET
Histogram view provides high level view of captured data Patented hardware search feature locates any PCI/X event in the trace buffer in seconds Logic analysis and PCI/X protocol analysis in the same compact unit
BUS DOCTOR? PCI/X ANALYZER
Protocol, Timing & Statistical Analysis Modular Bus Protocol Analyzer for PCI and PCI-X Buses OVERVIEW
The PCI (Peripheral Component Interconnect) architecture introduced by Intel in 1992 is the most common local I/O bus. It is the de facto standard for expansion slots in PCs, servers, and embedded designs. This parallel bus has been implemented in a variety of configurations and speeds. Originally designed to operate at 32-bits of data signals and a 33 MHz clock, later versions, such as PCI-X have introduced clock rates as high as 133 MHz permitting throughput rates of up to 1 GB/s at 64-bits. Designs and Engineers working with PCI technology will find a PCI protocol analyzer indispensable during the test and debug of this important bus type.
PRODUCT DESCRIPTION
The Bus Doctor? RX from Finisar is a powerful modular bus protocol Analyzer. With advanced features such as large trace buffers and 4 nanosecond capture resolution, the RX is a unique platform able to analyze PCI technology. Connecting a PCI/X Pod (available with 3.3V or 5V connectors) to a RX, the RX becomes a dedicated PCI or PCI-X (hereon both are called PCI/X) protocol Analyzer. The Analyzer is controlled by a Microsoft Windows? PC through a USB connection; Finisar?s powerful Bus Doctor Graphical User Interface (GUI) software runs on the PC. The software provides an easy-to-use interface that allows engineers to configure the instrument and to view and analyze captured PCI/X traffic. High-level dialogs provide for the quick creation of powerful triggers and pre- and post-capture filters. These filters allow engineers to home in, and capture and analyze only those events and sequences of interest. One can filter on pre-defined terms such as Idles and Transactions on specific addresses. Custom filters can also be set up. The powerful trigger sequencer has 12 levels, including 2 timer and 2 counter levels. This allows for triggering on Commands (e.g. Mem Read), Addresses (e.g. 32 or 64-bit) or Errors (e.g. Improper termination). Triggers may be setup for both hardware and software errors. Once data is captured, the software simplifies analysis by organizing and grouping the captured bus data into different displays.
